Efuses, as a type of one time program (OTP) devices, may be programmed to store data. Static random access memories (SRAMs) are one of the common types of memory, which utilize a static access method, and use bistable data latching circuits as memory cells. SRAMs have a high read speed. The efficiency of SRAMs can be increased without cooperating with the memory refreshing circuits. However, the integration level of SRAMs is low; and cannot save data when the power is off. When an integrated chip having an Efuse intellectual property (IP) core and a SRAM IP core is first powered-on, the SRAM IP core needs to read the backup data stored in the Efuse IP core, and the time for reading the backup data is usually referred to as the system powering-up time of the chips. The chips are often used as memory devices in cellular phones, and laptop computers, etc. When the cellular phones and the laptop computers are turned on, the chips read the stored backup data. Thus, the system powering-up time of the chips directly affects the powering-up time of the cell phones and the laptop computers, and directly affects the user experience.
The Efuse IP core in a chip includes a plurality of Efuse cell circuits. FIG. 1 illustrates an existing Efuse circuit structure. As shown in FIG. 1, the Efuse cell often includes a fuse 1 and an NMOS transistor M11. The fuse 1 is connected to the drain of the NMOS transistor M11. Because the programming current of the fuse 1 is relatively large, the NMOS transistor has a relatively large size. Such a large size causes the drain-gate load of the NMOS transistor to be relatively large; and its charging/discharging speed is relatively slow. Thus, the NMOS transistor M11 has a relatively slow switching speed. Such a relatively slow switching speed causes the NMOS transistor M11 to be unable to synchronize with the system clock; and increases the system powering-up time.
The SRAM IP core in the chip includes a plurality of SRAM cell circuits. The mainstream structure of the existing SRAMs includes six transistors; and is often referred to as 6T SRAMs FIG. 2 illustrates an existing 6T SRAM.
As shown in FIG. 2, the 6T SRAM includes six transistors: M21, M22, M23, M24, M25 and M26 The transistor M21 and the transistor M24 form a bistable data latch. The data latch has two branches and two latching nodes to latch the data needed to be latched by the 6T SRAM. The transistor M21 and the transistor M23 are often PMOS transistors; and the sources of the transistor M21 and the transistor M23 are both connected to the power source. The transistor M22 and the transistor M24 are often NMOS transistors; and the sources of the transistor M22 and the transistor M24 are both connected to ground. The transistor M25 and the transistor M26 are pass transistors; and a signal WL is inputted into the gate of the transistor M25 and the gate of the transistor M26. The signal WL is used to control the on/off of the transistor M25 and the transistor M26 The signal BL and the signal \BL are the output signals of the 6T SRAM
Thus, when the integrated chip having the Efuse IP core and the SRAM IP core is first powered-on, because the data reading by the SRAM IP core of the data stored in the Efuse IP core is unable to synchronize with the system clock, the system powering-up time is relatively long. Further, the MOS transistors in the chip take up relatively large areas. Thus, the area of the Efuse IP core is relatively large.
The disclosed Efuse bit cells and read/write methods thereof, and Efuse arrays are directed to solve one or more problems set forth above and other problems in the art.